| PART |
Description |
Maker |
| MX25R1035F |
Wide Vcc Range, 1M-BIT
|
Macronix International
|
| 5962-8876904KYA 5962-8876904KYC 5962-8876904KPA 59 |
5962-8876801PC · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876904KPA · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876904KXA · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876904KPC · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-88769022A · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876903FC · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876901PC · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876901PA · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876901XA · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876901YA · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876901YC · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
|
Agilent (Hewlett-Packard)
|
| 100393QC 100393 100393QCX |
Low Power 9-Bit ECL-to-TTL Translator with Latches
From old datasheet system
ECL-to-TTL Translator 9 ECL TO TTL TRANSLATOR, TRUE OUTPUT, PQCC28
|
FAIRCHILD[Fairchild Semiconductor]
Fairchild Semiconductor, Corp.
|
| VCUNCB-44.736 VDUNCB-44.736 VCLNCB-44.736 VDLNCB-4 |
VCXO, CLOCK, 3.686 MHz, CMOS/TTL OUTPUT
Voltage Controlled Crystal Oscillator
VCXO, CLOCK, 1.024 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 12.288 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 13 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 18.432 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 2 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 34.368 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 4 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 49.152 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 40.96 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 2.048 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 20.48 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 19.44 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 40 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 61.44 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 44.736 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 6.4 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 15.44 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 5 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 3.088 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 4.434 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 4.096 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 4.032 MHz, CMOS/TTL OUTPUT
VCXO, CLOCK, 1.544 MHz, CMOS/TTL OUTPUT
|
Vectron International, Inc
|
| UT61L256JC-10 UT61L256JC-12 UT61L256JC-15 UT61L256 |
Access time: 10 ns, 32 K x 8 Bit high speed low Vcc CMOS SRAM
Access time: 12 ns, 32 K x 8 Bit high speed low Vcc CMOS SRAM
Access time: 15 ns, 32 K x 8 Bit high speed low Vcc CMOS SRAM
Access time: 8 ns, 32 K x 8 Bit high speed low Vcc CMOS SRAM
|
UTRON Technology
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| VC120605D150D VA100026D580D |
DIODE SUPPRESS SMD GR1206 UNIDIR 5.6V
DIODE SUPPRESS AXIAL/BIPOL 26V MAX120A 二极管抑制轴双极26V的MAX120A
|
International Components, Corp.
|
| SP6137HCU SP6137HEU SP6137HV SP6137HCU_TR SP6137HE |
TRANS DUAL NPN 45V SOT-563
TRANSISTOR NPN BIPOL DFN1006-3
Dual Supply Synchronous Buck Controller
|
SIPEX[Sipex Corporation]
|
| AT20-0273 |
Digital Attenuator, 32 dB, 2-Bit, TTL Driver, DC - 2 GHz
ER 14C 12# 16 1#12 PIN RECP BO
Digital Attenuator/ 32 dB/ 2-Bit/ TTL Driver/ DC - 2 GHz
|
Tyco Electronics
|
| MC100H680 MC100H680FN MC10H680 MC10H680FN ON0804 M |
From old datasheet system
4-Bit Differential ECL Bus/TTL Bus Transceiver
4-Bit Differential ECL Bus/TTL Bus Transceciver
|
ONSEMI[ON Semiconductor]
Motorola, Inc
|
| 4559 M34559G6-XXXFP |
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 单芯位微机的CMOS
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
|
